182.695 Digital Design and Computer Architecture
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2024S, LU, 7.5h, 7.5EC


  • Semester hours: 7.5
  • Credits: 7.5
  • Type: LU Laboratory Exercise
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

  • develop combinatorial logic
  • implement simple state machines
  • introduce a pipelining concept in CPUs
  • carry out a synthesis and simulation of VHDL code in appropriate software tools
  • program an FPGA with the generated hardware
  • verify the hardware systematically using simulations, tests on the FPGA and measurements

Subject of course

Hands on application of the contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organization and Design"

  • design flow (synthesis & simulation)
  • testing & debugging of a VHDL design
  • handling digital measurement instruments
  • modern processor architecture

Teaching methods

  • Different tasks have to be solved autonomously
  • The used FPGA boards (Altera chips) are programmed using the synthesis software Quartus. For simulating the digital circuit the simulation tool Questa/Modelsim will be used (free for download on the web).
  • We provide a VM with all the required tools preinstalled.
  • The FPGA boards are programmed either directly in the TILab or using remote access to the TILab. A debug interface and a camera setup are used to observe the output of the FPGA boards.
  • Tutors will be available in the lab or over TU Chat and Zoom.
  • The exams take place in the lab


Mode of examination


Additional information

!!! The course starts with an introductory event on March 7 2024, 9:00 am in the lecture room FAV Hörsaal 1 - INF. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695) and “Hardware Modeling” (VO, 182.696) !!!

Please note that “Computer Organization and Design” (VO, 182.690) is not held in the sommer term 2024.

ECTS Breakdown

  6.0 h  Introduction lectures 
  3.0 h  Attendance Exercise Interviews
  8.0 h  Attendance Exams
170.5 h Task preparations
187.5 h (= 7.5 ECTS)



Course dates

Thu09:00 - 11:0007.03.2024FAV Hörsaal 1 Helmut Veith - INF Course Introduction (HWmod, DDCA)

Examination modalities

The final grade results from

  • performance in the four programming exams
  • the quality of the provided solutions to the assignments


DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Mon07:00 - 18:0003.06.2024TILab Raum 1 writtenunknownL3 Exam (Room Reservation)
Mon07:00 - 18:0003.06.2024TILab Raum 4 writtenunknownL3 Exam (Room Reservation)
Mon07:00 - 18:0003.06.2024TILab Raum 2 writtenunknownL3 Exam (Room Reservation)
Fri07:00 - 18:0028.06.2024TILab Raum 2 writtenunknownL4 Exam (Room Reservation)
Fri07:00 - 18:0028.06.2024TILab Raum 1 writtenunknownL4 Exam (Room Reservation)
Fri07:00 - 18:0028.06.2024TILab Raum 4 writtenunknownL4 Exam (Room Reservation)

Course registration

Begin End Deregistration end
15.02.2024 12:00 07.03.2024 10:00 07.03.2024 10:00


Study CodeObligationSemesterPrecon.Info
033 535 Computer Engineering Mandatory4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase


No lecture notes are available.

Previous knowledge

  • This course assumes that Hardware Modeling is done in parallel.
  • Basic programming knowledge (especially C)
  • Digital Design Basics
    • Combinational Logic: basic gates (AND, OR, XOR, etc.)
    • Sequential components (Flip-Flops, Latches)
    • Basic Boolean circuits
    • Memory (RAM/FIFO)
    • CMOS Basics (Driver, tri-state, pullup/pulldown resisitors, etc.)
    • Synchronizer
  • State Machines
    • Register. next-state/output logic
    • Moore vs. Mealy

Preceding courses

Accompanying courses

Continuative courses