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182.696 Hardware Modeling
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022S, VO, 1.5h, 1.5EC, to be held in blocked form
TUWEL

Properties

  • Semester hours: 1.5
  • Credits: 1.5
  • Type: VO Lecture
  • Format: Distance Learning

Learning outcomes

After successful completion of the course, students are able to

  • name the basic properties of hardware designs
  • apply basic VHDL commands and concepts
  • develop purely combinatorial logic, synchronous logic and logic with an internal state
  • formulate suitable solutions in VHDL to solve a given problem
  • develop a systematic plan for implementation and verification of a hardware design
  • identify design challenges and provide appropriate solutions

Subject of course

Hardware Development

  • motivation and introduction
  • key properties and differences to software design
  • challenges and hardware description languages

VHDL

  • entity, architecture and configuration
  • structural and behavioral programming
  • testbenches, components and packages
  • process, sensitivity list and control flow commands
  • state machines, three process method
  • data types, attributes, libraries, subprograms, ....

Hardware Modeling

  • design flow including verification
  • systematic and hierarchical designs, implementation and verification
  • circuit design challenges
  • state machine design
  • efficient and sustainable hardware description
  • synthesis and optimizations
  • functional/formal verification, automated testing

Tools

  • Quartus (synthesis)
  • Questasim (verification)

Teaching methods

Flipped Classroom Concept

  • content is presented in short videos, which can be consumed completely autonomously in the TUWEL course
  • short quizes and voluntary training examples support the learning process by giving immediate feedback
  • anonymous feedback and question to every video available
  • forum for exchange among students and for communication with the teaching staff
  • twice a week Zoom meeting for discussion of remaining questions

Mode of examination

Written

Additional information

Start of the lecture from February 22nd anytime individually possible! Visit the TUWEL course and get going!

  • heavily blocked at begin of semester to assure quick introduction to VHDL (required especially for LU Digital Design and Computer Architecture)
  • tools for simulation and synthesis are presented in the lecture

ECTS Breakdown

25 h    Videos and Quizes
12.5 h Continuous engagement with the lecture contents, preparation time for final exam
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37.5h  (= 1.5 ECTS)

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Important: Please ignore the recurring event 03.03.2022 - 23.06.2022 (08:00 - 10:00 Uhr). This entry is only there for internal organizational reasons.

The actual events are always Monday 16:00 (Zoom) and Thursday 09:00 (FAV Hörsaal 1).

!!! The course starts with an introductory event on 03.Mar.2022, 9:00 am. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695), “Hardware Modeling” (VO, 182.696) and “Computer Organization and Design” (VO, 182.690). !!!

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Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Thu08:00 - 10:0003.03.2022 - 23.06.2022FAV Hörsaal 1 - INF Lecture
Thu09:00 - 11:0003.03.2022 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Course Introduction (HWmod, DDCA, CA)
Mon16:00 - 17:0007.03.2022 - 28.03.2022 Zoom: https://tuwien.zoom.us/j/98129800147 (LIVE)Online Questions Session (Zoom)
Thu09:00 - 11:0010.03.2022 - 24.03.2022 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Questions Session
Hardware Modeling - Single appointments
DayDateTimeLocationDescription
Thu03.03.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu03.03.202209:00 - 11:00 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Course Introduction (HWmod, DDCA, CA)
Mon07.03.202216:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu10.03.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu10.03.202209:00 - 11:00 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Questions Session
Mon14.03.202216:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu17.03.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu17.03.202209:00 - 11:00 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Questions Session
Mon21.03.202216:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu24.03.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu24.03.202209:00 - 11:00 FAV Hörsaal 1: https://www.tuwien.at/index.php?id=1770Questions Session
Mon28.03.202216:00 - 17:00 Zoom: https://tuwien.zoom.us/j/98129800147Online Questions Session (Zoom)
Thu31.03.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu07.04.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu28.04.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu05.05.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu12.05.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu19.05.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu02.06.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Thu09.06.202208:00 - 10:00FAV Hörsaal 1 - INF Lecture
Course is held blocked

Examination modalities

Closed book exam on paper in presence (60 min).

Exams

DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Thu15:00 - 17:0001.12.2022 https://tuwien.zoom.us/j/97795674923?pwd=eGpZYzNiU2NoenF2U0VRanJxeDhQUT09written01.11.2022 00:00 - 29.11.2022 23:59TISSDezember
Mon14:00 - 15:0030.01.2023Informatikhörsaal - ARCH-INF written23.01.2023 00:00 - 29.01.2023 23:59TISSJan exam
Thu14:00 - 16:0002.03.2023EI 2 Pichelmayer HS - ETIT written14.02.2023 00:00 - 01.03.2023 23:59TISSMarch Exam
Tue13:00 - 14:0002.05.2023EI 9 Hlawka HS - ETIT written03.04.2023 12:00 - 01.05.2023 23:59TISSApril Exam (Haupttermin)

Course registration

Begin End Deregistration end
21.02.2022 00:00 03.04.2022 23:59

Curricula

Study CodeSemesterPrecon.Info
033 535 Computer Engineering 4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase

Literature

No lecture notes are available.

Previous knowledge

  • logic gates (OR, MUX, FF, etc.)
  • Mealy / Moore automata
  • Y-diagram
  • control flow concepts (if-then-else, loops, etc.)
  • synchronous circuit design
  • hardware design flow including verification

Preceding courses

Accompanying courses

Continuative courses

Miscellaneous

Language

English