After successful completion of the course, students are able to

• desrcibe the design and fabrication flows of a digital CMOS ASIC, justify their steps and list the challenges involved in them,
• correctly apply the abstraction of a field-effect transistor as a switch and use it to explain the basic function of simple logic gates
• describe implementation and operation of fundamental function blocks of digital logic, and apply them properly
• design a (combinational or simple sequential) digital circuit solving a given problem, and compare implementation options
• identify, in an application, the limits of the models and abstractions used in digital design, and appropriately account for them
• relate defects and functional faults in a digital integrated circuit to their potential cause in the design and fabrication flow, and describe the effect ot the most relevant parameters of influence in a qualitative and, where possible, a quantitative way.

• logic optimization
• structure and specifications of logic gates
• basic arithmetic circuits (adder, multiplier)
• I/O features (schmitt trigger, open collector, ...) 
• power dissipation and cooling 
• synchronous logic, limitations, state machines
• metastability
• memory types 
• VLSI design flow
• simulation of hardware
• target technologies for VLSI designs 
• chip manufacturing process 
• defects and testing

This is a classical lecture. The whole material is presented in lectures, in theory as well as with a relation to practical application. Example calculations are made during the lecture to facilitate the preparation for the final exam, and to show quantitative results and relations.Fundamental issues like the "speed signal propagation" are illustrated in experiments to allow for an intuitive understanding. The lecture slides including numerous animations are available on the homepage. For the preparation of the final exam a collection of past exams is also available.

Introductory lecture is on Oct 2, 10:15  online. You can find the link to the Zoom Meeting in TUWEL after course registration.

ECTS Breakdown:

36h ... lecture time
39h ... continuous engagement with the lecture contents, preparation time for final exam
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75h ... corresponding to 3ECTS

wirtten exam with theory questions and calculation-/design-assignments

Course registration will allow you access to the TUWEL course where you can find the lecture slides as well as the link to the online lecture.