After successful completion of the course, students are able to design and verify digitial integrated circuits in a team using state-of-the-art methods, and to package a design for re-usability and maintainance.

1. Describe the solution to a problem in a behavioral HDL
2. Learn to use the code of others
3. Learn what is important by using code of others: licensing, coding style, integration to your own code base
4. Create a self-contained package along with information necessary to be used by others
5. Learn to use several design tools for simulation and synthesis: Yosys, nextpnr, GHDL, GTKWave
6. Learn to automate tasks by scripting (Bash scripts, Makefiles, TCL scripts, ...)
7. Learn to collaborate, and to use tools that support collaboration (git, Telegram, ...)
8. Learn that it is not important to solve any problem strictly on your own, but that it is important to collaborate and to communicate in order to solve big problems
9. Learn that specifications never are complete (and that communication is important to make them complete for a limited scope)
10. Learn about licensing your own work

In the lab we will concuct a digital hardware design project in a team. The goal is to implement a specification, and to prove the implementation's correctness with formal verification methods.

Collaboration between colleagues is not only allowed, but encouraged. It is, however, not allowed to simply copy a design without knowing what is going on. This will be checked in the lab reviews.

The introductory session will be held on March 8, 09:00.

In the case of more registrations than places, students with an active relevant master degree (066 438, 066 439, 066 504, 066 507 and 066 508) are preferably admitted to students of other subjects. Within these groups the lot decides on the allocation of the space.

Continuous evaluation. Evaluation criteria are:

1. Understanding the implemented task
2. The solution's elegance
3. Group activity
4. Willingness to collaborate
5. Conformance to formal requirements

Lecture notes for this course are available. The actual versions can be accessed over TISS.

Knowledge in the following areas is advantageous:

1. Hardware description languages: VHDL, Verilog, SystemVerilog ASsertions (SVA), C++, Python, Bash
2. Formal modelling languages: SystemVerilog
3. EDA concepts: Modelling, synthesis, optimization, technology mapping, timing analysis, functional simulation, etc.
4. EDA tools: Yosys, nextpnr, icetime, Icarus Verilog, GHDL
5. Good understanding of digital system design, computer architecture