384.086 Digital Integrated Circuits
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2022W, VU, 2.0h, 3.0EC
TUWELLectureTube

Properties

  • Semester hours: 2.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise
  • LectureTube course
  • Format: Hybrid

Learning outcomes

After successful completion of the course, students are able to

-  Explain the ASIC and FPGA design process;

-  Demonstrate important synthesis algorithm such as logic synthesis and technology mapping;

-  Model, validate and implement simple designs on FPGAs;

-  Discuss the simulation and synthesis semantics of an HDL (VHDL or Verilog);

-  Design, simulate and validate HDL models for netlists, dataflow, processes and algorithms.

Subject of course

The course is based on the text book "Taking AIMS at Digital Design" by A. Jantsch. There is a link to the digital version of the book (see 'Litereature'). Additionally, all enrolled students can download lecture slides and supplimentary material in the course's download section.

The covered topics are: Modeling of digital circuits, a Hardware Description Langauge (HDL), logic optimization, mapping and implementation of digital design models, datapath models, Latches, Flip-Flops and Registers, synchronous design, synchronization, programmable logic, and other topcis of digital design.

Teaching methods

This year the class will be conducted in hybrid mode.

The theory will be studied before and during consolidation sessions and the practical skills will be acquired by solving practical examples in associated exercises.

Consolidation Sessions in the lecture room (or on-line)

The consodliation sessions are in the leture room or, if necessary, on-line. We use TUWEL as platform (and possibly Zoom).

All the course material, slides, and complementary material, will be provided in TUWEL.
Students prepare for the consolidation sessions by studying the material and formulating questions, which are then answered and discussed during the consolidation sessions.
For at least 80% of the sessions at least one question has to be formulated at least 24 hours bevore the corresponding session.

Exercises

The exercise consists of two parts:

  1. Design-time part: You model and verify a simple design and transform it into an FPGA bitstream step-by-step
  2. Run-time part: You run and verify your simple design on an FPGA platform

As HDL we use Verilog.

The exercises part will be fully held as a distance learning format. We'll have weekly video support sessions via Zoom (2h each), and e-mail support.

Mode of examination

Written and oral

Additional information

You must be enrolled to the course; this will entitle you to download the slides and to do the exercises (please note that you have to enroll to separate groups for the exercises).

This course is part of the Embedded Systems master program, in particular part of the SoC track. The Institute of Computer Technology offers several other relevant courses.

ECTS distribution:

15h ...   Participation in the consolidation sessions
12h ...   Preperation for the consolidation sessions
18h ...   VELS/Simulation exercises
10h ...   Labs
20h ...   Preparation for the exam
---------------
75h ...  3 ECTS credits in total

Lecturers

Institute

Course dates

DayTimeDateLocationDescription
Tue09:00 - 11:0004.10.2022 - 24.01.2023EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu13:00 - 14:0006.10.2022 - 01.12.2022 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09 (LIVE)Video support session
Digital Integrated Circuits - Single appointments
DayDateTimeLocationDescription
Tue04.10.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu06.10.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue11.10.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu13.10.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue18.10.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu20.10.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue25.10.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu27.10.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Thu03.11.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue08.11.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu10.11.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Thu17.11.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue22.11.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu24.11.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue29.11.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Thu01.12.202213:00 - 14:00 https://tuwien.zoom.us/j/92047143781?pwd=UzlpcjRGS0FBYUVCcTJOSFgyOWhvZz09Video support session
Tue06.12.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue13.12.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue20.12.202209:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation
Tue10.01.202309:00 - 11:00EI 8 Pötzl HS - QUER Lecture & Consolidation

Examination modalities

Consolidation Sessions

 As preperation for consolidation sessions students must prepare in the corresponding TUWEL forum

  • for at least 80% of the sessions
  • at least one subject-specific and meaningful question
  • at least 24 hours before the corresponding session.

I.e. if there are ten sessions, eight questions must be formulated at the very minimum.

The timely formulation of the minimum number of questions is a requirement for passing the exercise part of the class.

Exercises

  1. 7 VELS/simulation examples: 7 points each -> 49 points
  2. 1 FPGA lab: 51 points

You must at least get 51 points for the exercises to be entitled to do the exam.
Surplus points 52-100 will contribute to your final grade (max 49 points).

Exam

Exams will be held written or orally. The exam's mode is specific for a given exam date and will be announced in TISS.
You can only do an exam if you successfully passed the exercises.

You are allowed to use any printed material and a calculator, but no PC or laptop.

For the exam, you can get max 100 points.

Grading

The grading depends on the acquired points from exercises and exam. In total, you can get max 149 points.

0-74 points -> N5

75-93 points -> G4

94-112 points -> B3

113-131 points -> U2

132-149 points -> S1

Exams

DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Mon16:00 - 18:0022.04.2024 Büro Jantschoral30.03.2024 11:00 - 11.04.2024 23:59TISSDIS Prüfung (Stoff WS 2023)
Mon15:00 - 17:0013.05.2024 Büro Jantschoral15.04.2024 23:59 - 09.05.2024 23:59TISSDIS Prüfung (Stoff WS 2023)

Course registration

Begin End Deregistration end
01.09.2022 12:00 09.10.2022 12:00 09.10.2022 12:00

Curricula

Study CodeObligationSemesterPrecon.Info
066 438 Computer Technology Not specified1. Semester
066 439 Microelectronics Not specified1. Semester
066 504 Master programme Embedded Systems Mandatory1. Semester
066 507 Telecommunications Mandatory
066 508 Microelectronics and Photonics Mandatory1. Semester

Literature

Axel Jantsch, Taking AIMS at Digital Design, TU Verlag, 2022. (Available from the TU Verlag)

Continuative courses

Language

if required in English