After successful completion of the course, students are able to
- Explain the ASIC and FPGA design process;
- Demonstrate important synthesis algorithm such as logic synthesis and technology mapping;
- Model, validate and implement simple designs on FPGAs;
- Discuss the simulation and synthesis semantics of an HDL (VHDL or Verilog);
- Design, simulate and validate HDL models for netlists, dataflow, processes and algorithms.
The course is based on the text book "Lehrbuch Digitaltechnik" by Jürgen Reichardt. There is a link to the digital version of the book (see 'Litereature'). Additionally, all enrolled students can download lecture slides and supplimentary material in the course's download section.
The covered topics are: Modeling of digital circuits, a Hardware Description Langauge (HDL), logic optimization, mapping and implementation of digital design models, datapath models, Latches, Flip-Flops and Registers, synchronous design, synchronization, programmable logic, and other topcis of digital design.
This year the class will be conducted in hybrid mode.
The theory will be studied before and during consolidation sessions and the practical skills will be acquired by solving practical examples in associated exercises.
The consodliation sessions are online or in the lecture room. We use Zoom and TUWEL.
All the course material, slides, video clips and complementary material, will be provided in TUWEL.Students prepare for the consolidation sessions by studying the material and formulating questions, which are then answered and discussed during the consolidation sessions.For at least 80% of the sessions at least one question has to be formulated at least 24 hours bevore the corresponding session.
The exercise consists of two parts:
As HDL we use Verilog.
The exercises part will be fully held as a distance learning format. We'll have weekly video support sessions via Zoom (2h each), and e-mail support.
You must be enrolled to the course; this will entitle you to download the slides and to do the exercises (please note that you have to enroll to separate groups for the exercises).
This course is part of the Embedded Systems master program, in particular part of the SoC track. The Institute of Computer Technology offers several other relevant courses.
ECTS distribution:
15h ... Participation in the consolidation sessions12h ... Preperation for the consolidation sessions18h ... VELS/Simulation exercises10h ... Labs20h ... Preparation for the exam---------------75h ... 3 ECTS credits in total
As preperation for consolidation sessions students must prepare in the corresponding TUWEL forum
I.e. if there are ten sessions, eight questions must be formulated at the very minimum.
The timely formulation of the minimum number of questions is a requirement for passing the exercise part of the class.
You must at least get 51 points for the exercises to be entitled to do the exam. Surplus points 52-100 will contribute to your final grade (max 49 points).
Exams will be held written or orally. The exam's mode is specific for a given exam date and will be announced in TISS. You can only do an exam if you successfully passed the exercises.
You are not allowed to use any material (not even a calculator).
For the exam, you can get max 100 points.
The grading depends on the acquired points from exercises and exam. In total, you can get max 149 points.
0-74 points -> N5
75-93 points -> G4
94-112 points -> B3
113-131 points -> U2
132-149 points -> S1
Registration is necessary to successfully complete the course, to download the slides and attend the labratories.
Reichardt, Jürgen, Lehrbuch Digitaltechnik, Oldenbourg Verlag, 2013.
Kesel, Frank / Bartholomä, Ruben, Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs, Oldenbourg Verlag, 2013
