182.756 Advanced FPGA Design
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2023W, VU, 3.0h, 3.0EC


  • Semester hours: 3.0
  • Credits: 3.0
  • Type: VU Lecture and Exercise
  • Format: Presence

Learning outcomes

After successful completion of the course, students are able to manage advanced FPGA design aspects related to  timing, area, power constraints analysis and optimization.  Partial reconfiguration, run time reconfiguration techniques and applications will be studied. Design for synthesis is introduced through different experimental applications.

Subject of course

Course Description

The course introduces advanced FPGA design techniques. Emphasis is placed on timing, area, power constraints analysis and optimization. Partial reconfiguration, run time reconfiguration techniques and applications will be studied. Design for synthesis is introduced through different experimental applications. Design verification methodologies will be investigated. Hands on experiments using both design and simulation software tools and FPGA demonstration boards will be designed to explore the introduced topics.

 Course Outline s (2 hours per week for 10 weeks + one week for the final exam)

-       Speed Optimization (1 Week)

  • Throughput
  • Latency
  • Delay paths
  • Clock Domains

-       Area Optimization (1 Weeks)

  • Rolling the pipeline
  • Logic reuse
  • Sharing Logic resources
  • Reset circuits

-       Power Optimization (1 Week)

  • Clock control and dynamic power consumption
  • Clock gating
  • Input control for power minimization

-       Design for Synthesis (2 Weeks)

  • Synthesis optimization
  • Tradeoffs
  • Floorplanning
  • Place and route optimization

-       Partial Reconfiguration (1 Week)

  • Concept and techniques
  • Partial reconfiguration for area and power optimization
  • Partial reconfiguration for fault tolerance

-       Simulation and verification (2 Weeks)

  • Advanced simulation techniques
  • Formal verification techniques
  • Universal Verification Methodology (UVM)


Security in FPGAs (1 Week) 


Reliability of FPGAs (1 Week)



Teaching methods

Lecture sessions

Investigating and developing projects for FPGA design flow

Mode of examination

Written and oral

Additional information

An overview and introduction to this course (as well as other Master courses offered by the ECS group) will be given on

Oct 3rd 2023 at 9:15 in the Seminar room Treitlstrasse 3, 2nd floor.  https://tuwien.zoom.us/j/99102860102


ECTS breakdown:

20h ...   presence in the lectures
40h ...   solution of the design problems
15h ...   preparation for the exam
75h ...  equals 3 ECTS



Course dates

Tue16:00 - 18:0010.10.2023 - 16.01.2024Seminarraum 384 Lecture
Advanced FPGA Design - Single appointments
Tue10.10.202316:00 - 18:00Seminarraum 384 Lecture
Tue24.10.202316:00 - 18:00Seminarraum 384 Lecture
Tue31.10.202316:00 - 18:00Seminarraum 384 Lecture
Tue07.11.202316:00 - 18:00Seminarraum 384 Lecture
Tue14.11.202316:00 - 18:00Seminarraum 384 Lecture
Tue28.11.202316:00 - 18:00Seminarraum 384 Lecture
Tue05.12.202316:00 - 18:00Seminarraum 384 Lecture
Tue19.12.202316:00 - 18:00Seminarraum 384 Lecture
Tue09.01.202416:00 - 18:00Seminarraum 384 Lecture
Tue16.01.202416:00 - 18:00Seminarraum 384 Lecture

Examination modalities


The course grade will be based on practical design projects and two exams.


Grading Weights:

  • Mid-term Exam: 15 %.
  • Four practical design projects each will be graded with 15%.
  • Final Exam: 25%.

Course registration

Begin End Deregistration end
28.07.2023 00:00 23.10.2023 16:00 23.10.2023 23:00


Study CodeObligationSemesterPrecon.Info
066 938 Computer Engineering Mandatory elective


No lecture notes are available.

Preceding courses

Continuative courses