The aim of the course is on the FPGA implementation of complex algorithms under strict requirements, as well as different aspects of FPGA synthesis. Students shall attain the ability to solve complex design problems for FPGAs with recent technology, on their own.

The course starts with an overview of various aspects of FPGA design and continues with a focus on

a) efficient FPGA design for fast complex algorithms; synchronous pipeline

b) FPGA design flow from coding techniques over simulation to synthesis including place & route

c) optical link in FPGA Virtex 6/7: implementation, robustness test

d) complex contemporary hardware with modular structure (e.g. from telecom area)

A specific focus will be on synthesis, timing constraints, the testbench, partial reconfiguration, robustness of the FPGA design as well as the concept of testability.

ECTS Aufstellung:

12h ... presence in the lecture: 4 blocks 3 hours each
20h ... weekly meetings: 10 blocks 2 hours each
  5h ... presentations & demo of design
38h ... project work + documentation
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75h ... total

didactic concept:

lecture blocks, solving concrete design problems in a group, continuous presentation of intermediate results, discussion of problems, presentation and defense of final result