the following competences shall be conveyed:

• deal with challenging (timing) issues in digital design (esp. clock domain crossing)
• understand the theoretical underpinningsof the synchronous design style and its alternatives
• choose and apply the appropriate style for a given problem
• understand the involved limitations

• basic concept and limitations of synchronous design
• metastability: causes and effects, modelling, MTBU estimation and measurement
• design and implementation of synchronizers for different settings
• GALS-Systems (timing domain crossing, pausable clocking)
• internal design, function and limitations of the basic building blocks of asynchronous design: Muller C-Element and Mutual Exclusion Element
• asynchronous design methods (bundled data, delay insensitive), handshake principles (2-phase/4-phase) and timing models (bundled data, delay insensitive,...)
• fundamental description methods for asynchronous design
• comparison of synchronous and asynchronous logic

The course comprises lectures as well as several blocks during which exercises and design problems that have been assigned as homework are discussed. The overall grading considers contributions made during the lectures and the discussion blocks, the quality of the homeworks with exercises (30%) and labs (35%), and the performance in a final written exam (35%).

The didactic concept comprises a mix of classic lecture for conveying the basics, exercises for a first application of the material, as well as some design problems for the application of the knowlede in a practical setting (and partly an extension through self-study). This will put the graduate in the position to directly and effectively apply the acquired skills in practice.

Preliminary lecture on 5.10.2016 at 9:15 in HS4