After successful completion of the course, students are able to
Solution of a practical assignment from the field of HW-SW codesign - design, commissioning and optimisation of a complete system consisting of a processor, self-designed HW modules (FPGA), software (including drivers). Examples of necessary steps are:
The students learn to handle the soft-core processor Nios II from Intel and the corresponding tools such as the Platform Designer and Quartus. There is furthermore a major focus on giving the students a lot of room to make their own decisions.
An overview and introduction to this course (as well as other Master courses offered by the ECS group) will be given on
Oct 5th 2022 at 9:15 in the seminar room DE0110 (Treitlstrasse 3, 1st floor)
ECTS Breakdown
98.5 h Solving the task assignments 4 h Preparation of the mid-term presentation 4 h Preparation of the final presentation 6 h Presence at the presentations/exercise interviews-----------------------------------------------112.5 h ( = 4.5 ECTS)
demonstration of the acchieved solution to the supervisor and defence of implemenation detailspresentation of a proper concept to the remaining groups and discussion of chosen design decisions.
This course will be held in a hybrid form. The Lectures and meetings will, be held in presence at the university (if possible). Exercise interviews are held online (a webcam is required for identity verification).For the initial phase of the course (non-group phase) a remote access to the required hardware (FPGA development board ) is provided. For the group-phase one FPGA board per group can be borrowed. Physical access to the computer lab (TILab) will be provided!
