182.696 Hardware Modeling
This course is in all assigned curricula part of the STEOP.
This course is in at least 1 assigned curriculum part of the STEOP.

2021S, VO, 1.5h, 1.5EC, to be held in blocked form
TUWELQuinn ECTS survey


  • Semester hours: 1.5
  • Credits: 1.5
  • Type: VO Lecture
  • Format: Online

Learning outcomes

After successful completion of the course, students are able to

  • name the basic properties of hardware designs
  • apply basic VHDL commands and concepts
  • develop purely combinatorial logic, synchronous logic and logic with an internal state
  • formulate suitable solutions in VHDL to solve a given problem
  • develop a systematic plan for implementation and verification of a hardware design
  • identify design challenges and provide appropriate solutions

Subject of course

Hardware Development

  • motivation and introduction
  • key properties and differences to software design
  • challenges and hardware description languages


  • entity, architecture and configuration
  • structural and behavioral programming
  • testbenches, components and packages
  • process, sensitivity list and control flow commands
  • state machines, three process method
  • data types, attributes, libraries, subprograms, ....

Hardware Modeling

  • design flow including verification
  • systematic and hierarchical designs, implementation and verification
  • circuit design challenges
  • state machine design
  • efficient and sustainable hardware description
  • synthesis and optimizations
  • functional/formal verification, automated testing


  • Quartus (synthesis)
  • Questasim (verification)

Teaching methods

Flipped Classroom Concept

  • content is presented in short videos, which can be consumed completely autonomously in the TUWEL course
  • short quizes and voluntary training examples support the learning process by giving immediate feedback
  • anonymous feedback and question to every video available
  • forum for exchange among students and for communication with the teaching staff
  • twice a week Zoom meeting for discussion of remaining questions

Mode of examination


Additional information

Start of the lecture from February 22nd anytime individually possible! Visit the TUWEL course and get going!

  • heavily blocked at begin of semester to assure quick introduction to VHDL (required especially for LU Digital Design and Computer Architecture)
  • tools for simulation and synthesis are presented in the lecture

ECTS Breakdown

25 h    Videos and Quizes
12.5 h Continuous engagement with the lecture contents, preparation time for final exam
37.5h  (= 1.5 ECTS)



Course dates

Mon16:00 - 17:0001.03.2021 - 22.03.2021 https://tuwien.zoom.us/j/94528375642?pwd=MG9TQXl6TUllQU0zbVpTV0hYK3JqQT09 (LIVE)Presence Phase
Thu09:00 - 10:0004.03.2021 - 25.03.2021 https://tuwien.zoom.us/j/99530733562?pwd=WDVzU2txeS9hRmNBYzA0WU8yck5nQT09 (LIVE)Presence Phase
Hardware Modeling - Single appointments
Mon01.03.202116:00 - 17:00 https://tuwien.zoom.us/j/94528375642?pwd=MG9TQXl6TUllQU0zbVpTV0hYK3JqQT09Presence Phase
Thu04.03.202109:00 - 10:00 https://tuwien.zoom.us/j/99530733562?pwd=WDVzU2txeS9hRmNBYzA0WU8yck5nQT09Presence Phase
Mon08.03.202116:00 - 17:00 https://tuwien.zoom.us/j/94528375642?pwd=MG9TQXl6TUllQU0zbVpTV0hYK3JqQT09Presence Phase
Thu11.03.202109:00 - 10:00 https://tuwien.zoom.us/j/99530733562?pwd=WDVzU2txeS9hRmNBYzA0WU8yck5nQT09Presence Phase
Mon15.03.202116:00 - 17:00 https://tuwien.zoom.us/j/94528375642?pwd=MG9TQXl6TUllQU0zbVpTV0hYK3JqQT09Presence Phase
Thu18.03.202109:00 - 10:00 https://tuwien.zoom.us/j/99530733562?pwd=WDVzU2txeS9hRmNBYzA0WU8yck5nQT09Presence Phase
Mon22.03.202116:00 - 17:00 https://tuwien.zoom.us/j/94528375642?pwd=MG9TQXl6TUllQU0zbVpTV0hYK3JqQT09Presence Phase
Thu25.03.202109:00 - 10:00 https://tuwien.zoom.us/j/99530733562?pwd=WDVzU2txeS9hRmNBYzA0WU8yck5nQT09Presence Phase
Course is held blocked

Examination modalities

Closed book exam on paper during web meeting. After the exam you have to scan your solution and upload it to TUWEL. At least a webcam, a printer and the possibility to scan your solution (scanner, smartphone, ...) are required.


DayTimeDateRoomMode of examinationApplication timeApplication modeExam
Wed10:00 - 12:0005.07.2023Informatikhörsaal - ARCH-INF written19.05.2023 08:00 - 04.07.2023 23:59TISSEnd of SS23
Thu14:00 - 16:0007.03.2024EI 2 Pichelmayer HS - ETIT written20.02.2024 00:00 - 06.03.2024 23:59TISSMarch Exam
Thu09:00 - 10:0004.04.2024FAV Hörsaal 1 - INF written07.03.2024 00:00 - 03.04.2024 23:59TISSHaupttermin

Course registration

Begin End Deregistration end
22.02.2021 00:00 04.04.2021 23:59


Study CodeObligationSemesterPrecon.Info
033 535 Computer Engineering Mandatory4. SemesterSTEOP
Course requires the completion of the introductory and orientation phase


No lecture notes are available.

Previous knowledge

  • logic gates (OR, MUX, FF, etc.)
  • Mealy / Moore automata
  • Y-diagram
  • control flow concepts (if-then-else, loops, etc.)
  • synchronous circuit design
  • hardware design flow including verification

Preceding courses

Accompanying courses

Continuative courses