After successful completion of the course, students are able to

• develop combinatorial logic
• implement simple state machines
• introduce a pipelining concept in CPUs
• carry out a synthesis and simulation of VHDL code in appropriate software tools
• program an FPGA with the generated hardware
• verify the hardware systematically using simulations, tests on the FPGA and measurements

Hands on application of the contents of the lectures "Digital Design", "Hardware Modeling" and "Computer Organization and Design"

• design flow (synthesis & simulation)
• testing & debugging of a VHDL design
• handling digital measurement instruments
• modern processor architecture

• Different tasks have to be solved autonomously/in groups
• The used FPGA boards (Altera chips) are programmed using the synthesis software Quartus. For simulating the digital circuit the simulation tool Questa/Modelsim will be used (free for download on the web).
• We provide a VM with all the required tools preinstalled.
• The FPGA boards are programmed either directly in the TILab or using remote access to the TILab. A debug interface and a camera setup are used to observe the output of the FPGA boards.
• Tutors will be available in the lab or over TU Chat and Zoom.
• Both the midterm and the final exam will take place in the lab.

In case switching from classroom teaching to online teaching is required, the following changes will be made:

• The access to the FPGA boards will only be possible via the remote setup
• Tutors will only be available via TU chat and Zoom
• Exams: Will take place in the lab as soon as accessing the lab is possible

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!!! The course starts with an introductory event on 03.Mar.2022, 9:00 am. It is a joint event covering the courses “Digital Design and Computer Architecture” (LU, 182.695), “Hardware Modeling” (VO, 182.696) and “Computer Organization and Design” (VO, 182.690). !!!
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ECTS Breakdown

2.5 h   Introduction lecture 
 90 h   Tasks first part (Digital design basics)
 10 h   Preparation for midterm exam
 75 h   Tasks second part (Computer architecture)
 10 h   Preparation for final exam
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 187.5 h (= 7.5 ECTS)

The final grade results from

• the quality of the provided solutions to the assignments
• performance in the two written exams in the middle and at the end of the semester